package CPU.rv64_1stage
import chisel3._
import chisel3.util.experimental.BoringUtils
class InstFetch extends Module{
  val io = IO(new Bundle{
      val imem  = new RomIO
      val pc    = Output(UInt(32.W))
      val inst  = Output(UInt(32.W))
      val isbran= Input(Bool())
      val branpc= Input(UInt(32.W))
  })
  val pc         = RegInit("h80000000".U(32.W))
  val pc_valid   = RegInit(false.B)
  val next_pc    = Mux(io.isbran,io.branpc,pc+4.U)
  pc_valid      := true.B
  pc            := Mux(pc_valid,next_pc,pc)
  io.imem.en    := pc_valid
  io.imem.addr  := pc

  io.pc   := pc
  io.inst := io.imem.rdata(31,0)
  BoringUtils.addSource(pc_valid, "pc_valid")
}
